Integrated circuits ("ICs") are fabricated layer-by-layer on a semiconductor substrate, with bond wires coupling V.sub.SS, V.sub.DD, and input/output signals between pads on the upper surface of the substrate and the IC package. Generally there will be many V.sub.SS and V.sub.DD pads on the periphery of the IC. For example, an IC having 300 pin-outs may have 100 peripheral bonding pads dedicated to V.sub.SS and/or V.sub.DD. Bond wires couple these peripheral pads to on-chip V.sub.SS and V.sub.DD power rails.
With reference to FIG. 1, using techniques well known in the art of semiconductor fabrication, metal-oxide-semiconductor ("MOS") transistors, bipolar transistors, diodes and other devices 10 are fabricated and combined to form an IC, shown generically as 12, on a substrate 14. Typically, portions of some of the devices and some interconnections are frequently formed using one more levels of polysilicon. For example, in FIG. 1, a MOS transistor gate electrode 16, and a resistor 18 are depicted as being fabricated from a first layer of polysilicon.
Other interconnections to IC 12 may be made using overlying levels of metallization, for example metal 1 layer trace 20, metal 2 layer trace 22 and perhaps metal 3 layer trace 24. For an IC with three layers of metallization various metal 1 layer traces usually are coupled to the upper power supply V.sub.DD, the metal 2 layer traces carry signals, and various metal 3 layer traces are coupled to the lower power supply V.sub.SS (usually ground). For an IC with only two layers of metallization, various metal 1 layer traces are typically coupled to V.sub.SS, while some metal 2 layer traces will carry V.sub.DD and others will carry signals. These generalizations are not absolute, however, and V.sub.DD and/or V.sub.SS traces may be formed at any level of metallization in an IC, including a common level of metallization.
As shown in FIG. 1, an inter-level dielectric isolation ("ILD") layer 26 is formed between the metal 1 layer 20 and the uppermost polysilicon layer, here comprising segments 16 and 18. The ILD layer 26 typically includes boron phosphorus silicate glass ("BPSG") and insulates the polysilicon layer segments from metal 1 segments.
Inter-metal oxide ("IMO") layers 28, 30 are formed between adjacent levels of metallization. To help smooth out the otherwise bumpy topology, the IMO layers typically include spun-on-glass ("SOG"), which is applied in liquid form.
A relatively hard, outermost passivation layer 32 protects the underlying layers comprising the IC. Typically, passivation layer 32 includes silicon nitride and is formed using plasma enhanced chemical vapor deposition techniques.
Electrical connections between the various metallization layers 20, 22, and (if present) 24 and regions of IC 12 are made using conductive vias, e.g., 34, 36, which vias are depicted as terminating at bond pads 38, 40. It is understood that there will be many V.sub.SS traces, all of which will be electrically coupled together and to V.sub.SS through one or more peripheral V.sub.SS bonding pads and bond wires. Similarly, there will be many V.sub.DD traces, all of which will be electrically coupled together and to V.sub.DD through one or more peripheral V.sub.DD bonding pads and bond wires.
For ease of comprehension, FIG. 1 shows bond wires 42, 44 respectively connecting V.sub.SS and V.sub.DD to pads 38 and 40 and (in this example) to V.sub.SS trace 24 and V.sub.DD trace 20. In practice, however, bond wires 42 and 44 will be connected to peripheral bond pads, whereas pads 38 and 40 may be formed other than on the periphery of IC 12. Further, FIG. 1 does not show other vias that may be used to couple signals from various metal traces to the surface of the passivation layer 32, wherefrom the signals may be coupled elsewhere.
Thus, in the three metal layer embodiment of FIG. 1, it is understood that various of the metal 1 level traces typically will be coupled to V.sub.DD, and that various of the metal 3 level traces typically will be coupled to V.sub.SS. When IC 12 is actually used, power supplies providing V.sub.SS and V.sub.DD will be coupled to connector pins (not shown) on the package encapsulating IC 12. Connections from these pins are made with bond wires 42, 44 to peripheral V.sub.SS and V.sub.DD bonding pads and power rails on IC 12.
Those skilled in the art of circuit design will appreciate that reliable IC operation dictates that the V.sub.SS and V.sub.DD voltage levels seen by IC 12 be as noise-free as possible. By noise-free it is meant that ideally the V.sub.SS and V.sub.DD signals on the IC traces are pure DC, with no AC transient components.
Unfortunately, AC switching noise components are generally present. These noise components can arise from imperfect switching of complementary MOS inverters, wherein pull-up and pull-down transistors are simultaneously on during output state transitions. Further, unavoidable inductance (L) effectively in series with IC bond wire leads, e.g., leads 42, 44 can produce ground bounce. Ground bounce can produce current slewrate (L di/dt) changes in voltages coupled to IC 12, including V.sub.SS and V.sub.DD. Crosstalk between adjacent signal traces can also couple switching noise to traces carrying V.sub.SS or V.sub.DD.
It is known to reduce switching noise by providing a bypass capacitor 50 at the surface of an IC, coupled between IC pads carrying V.sub.SS and V.sub.DD. Several techniques for providing on-chip bypassing are described in the reference The Close Attached Capacitor: A Solution to Switching Noise Problems by S. H. Hashemi, et al. 0148-6411/92 p. 1056-1063 (1992).
Bypass capacitor 50 is frequently in the 1 nF to 100 nF range, and may occupy an area of perhaps 0.050" by 0.1" (1.3 mm by 2.6 mm). Typically, bond wires 52, 54 couple capacitor 50 to IC bonding pads, e.g., 38, 40. Unfortunately, these capacitor bond wires have an excessively large effective series inductance of perhaps 2-5 nH.
Thus, the effectiveness of the bypass capacitor is degraded by the series inductance contributed by the capacitor bond wires. As a result, excessive switching noise can remain on the V.sub.DD and/or V.sub.SS IC traces.
In short, there is a need for a more effective method of providing on-chip capacitor bypassing to reduce switching noise within an integrated circuit. Preferably such method should be implemented using standard IC fabrication processes.
The present invention provides such a method.